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Authors: Kumud Bhandari, Vivek Sarkar
DFM'16: Proceedings of the Sixth Workshop on Data-Flow Execution Models for Extreme Scale Computing
Article No.: 2, Pages 1 - 8
Published: 15 September 2016 Publication History
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Abstract
As the DRAM technology is fast reaching a scaling threshold, emerging non-volatile, byte-addressable memory (NVRAM) is expected to supplement and eventually replace DRAM. Future computing systems are anticipated to have a large amount of NVRAM, possibly spanning across more than one coherence domain. Furthermore, taking advantage of in-place persistence provided by the NVRAM in future systems requires a strategy to prevent tolerated failures (e.g. power failure) from leaving persistent data in an incoherent state. A fresh look at memory management approaches across the system stack is required to fully utilize future NVRAM. In this paper, we carefully assess the NVRAM-related memory access and management challenges, its implication to application level programming, and examine the suitability of tree-based read-only data chunks to NVRAM programming.
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Tree-based Read-only Data Chunks for NVRAM Programming
Software and its engineering
Software organization and properties
Contextual software domains
Operating systems
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Published In
DFM'16: Proceedings of the Sixth Workshop on Data-Flow Execution Models for Extreme Scale Computing
September 2016
30 pages
ISBN:9781450361996
DOI:10.1145/3292533
Copyright © 2016 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [emailprotected]
Sponsors
- IFIP WG 10.3: IFIP WG 10.3
- SIGARCH: ACM Special Interest Group on Computer Architecture
- IEEE CS TCPP: IEEE Computer Society Technical Committee on Parallel Processing
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Association for Computing Machinery
New York, NY, United States
Publication History
Published: 15 September 2016
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Author Tags
- NVM
- NVRAM
- data persistency
- failure resilience
- memory model
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- Research-article
- Research
- Refereed limited
Conference
PACT '16
Sponsor:
- IFIP WG 10.3
- SIGARCH
- IEEE CS TCPP
PACT '16: International Conference on Parallel Architectures and Compilation
September 15, 2016
Haifa, Israel
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